ASPDAC06-NAIST A Memory Grouping Method for Sharing Memory BIST Logic

Abstract - With the increasing demand for SoCs to include rich
functionality, SoCs are being designed with hundreds of small
memories with different sizes and frequencies.

This paper proposes a memory-grouping method for memory BIST logic
sharing.

I. Introduction
With the increasing number of functions being included in
SoCs, many memories with different sizes and frequencies
are being used.

A BIST architecture, based on a single
micro-programmable BIST processor and a set of memory
wrappers, was proposed to simplify the testing of systems
containing many distributed SRAMs of different sizes [1].

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In this paper, we propose two types of memory-connection methods for BIST wrapper sharing

II. Memory BIST Logic sharing
In this section, we describe our method of BIST logic
sharing for single port and word access memory
(The area of the address generator, data generator, and
response analyzer are almost proportional to the bit width of
the address, input data, and output data,)

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